PLATFORM

POWER MANAGEMENT

Bringing overall power consumption down to 1/10th of typical power consumed

Ineda’s SoCs are designed for power-sensitive IoT and Automotive applications. There are various design techniques implemented in the Ineda’s SoCs that bring the overall power consumption down to 1/10th of typical power consumed by a Big-Medium-Little-Tiny implementation of processor architecture. These design techniques include:

- Architecture-Level:
   > Contributed by Hierarchical computing and I/O virtualization technologies

- Hardware System-Level:
   > Power and clock gating, multiple power domains, adaptive power scaling of memory and peripherals.

- Software APIs:
   > Power and performance states selection of System, CPU and Peripheral States

   > On-demand clocking and frequency scaling controls

The Power states are mainly classified into three categories; Peripheral/Device Power states (denoted as D-states), CPU Power states (denoted as C-states) and the system power states (denoted as S-states). The D-states and C-states are almost similar except for possible H/W event triggered transition from low power states to active states in case of C-states. The system power states control the frequency scaling and power gating for each of the component in the SoC.

A separate power management block inside the Always-ON Sub-system handles clock gating, power gating and frequency scaling. The state selection and control is available as API hooks to the user to build an application algorithmic flow according to his/her power budget.

Highlight of low power architecture and power management block:

  • Separate voltage rails for different hierarchies of CPUs, Memory and associated peripherals.
  • Multiple Power islands within each subsystem driven by independent voltage rates.
  • Capability to Turn-On / Turn-Off SoC Core power rails
  • Controlling the shut-down and power-on sequences (including system reset sequence)
  • Sensor Sub-system Isolation from rest of the core
  • Always-On Sensor IO Pads for un-interrupted usage
  • Sensor On/Off Island power gating
  • Dynamic frequency scaling
  • Coarse grain clock gating for various modules
  • “Halt” instruction clock gating for lowest CPU core
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